1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory (EEPROM) capable of electrically rewriting/erasing information.
2. Description of the Related Art
The stored information rewrite operations of nonvolatile semiconductor memories are roughly classified into operations performed by a scheme (1) of writing information with hot electrons and erasing information with a tunnel current and operations performed by a scheme (2) of writing information with a tunnel current and erasing information with a tunnel current.
A flash EEPROM is a typical example of the nonvolatile semiconductor memory using the former scheme (1). In the flash EEPROM, information is written by applying a write voltage (high voltage Vpp) to both the control gate and drain electrode of a MOS transistor constituting a memory cell and injecting hot electrons into the floating gate.
In such an EEPROM, the threshold of a memory cell transistor changes with a change in the channel length of a MOS transistor for a memory cell, the thickness of the tunnel current passage insulating film (the thickness of the tunnel oxide film) under the floating gate, the electrode voltage between the source and the drain, or the like. As a result, the distribution (data "0") of threshold voltage VTH after information is written in each memory cell transistor greatly varies, as indicated by the hatched upper distribution in FIG. 7A or 7B.
In an erase operation, the control gate of a MOS transistor for a memory cell is grounded, and an erase voltage (Vpp) is applied to the source electrode (or the drain electrode), thereby extracting the electrons trapped in the floating gate to the source electrode (or the drain electrode) in the form of a tunnel current. In this erase operation as well, the distribution (data "1") of threshold voltage VTH of the memory cell after the information is erased is dependent on variations in the voltage (word line voltage) of the control gate, the drain voltage (or the bit line voltage), the thickness of the tunnel oxide film, or the like, and hence greatly varies, as indicated by the hatched lower distribution in FIG. 7A or 7B.
A NAND type EEPROM is a typical example of the nonvolatile semiconductor memory using the latter scheme (2). In the NAND type EEPROM, information is written or erased with a tunnel current from the floating gate of a MOS transistor constituting a memory cell.
The tunnel current used in the scheme (2) varies depending on variations in word line voltage (control gate voltage), bit line voltage (drain voltage), or the thickness of a tunnel oxide film, as in the erase operation performed by the scheme (1) described above. For this reason, in the scheme (2) as well, the distribution of threshold voltage VTH of a memory cell transistor in a write/erase operation greatly varies, as indicated by the hatched upper/lower distribution in FIG. 7C.
For example, in the case shown in FIG. 7B, of the variations in threshold voltage VTH, since variations on the upper voltage side (data "0" write operation) are distributed on the side higher than the read voltage (+5 V of TTL level) of the EEPROM, no significant problem is posed. However, since variations in threshold voltage VTH on the lower voltage side (data "1" erase operation) are distributed on the side lower than the read voltage (+5 V of TTL level) of the EEPROM, a data read operation is greatly influenced by the variations.
More specifically, if threshold voltage VTH (in particular, a threshold set after the electrons in the floating gate are extracted in an erase operation) of a memory cell transistor constituting the EEPROM greatly varies as described above, it is possible not to perform an information read operation based on a predetermined threshold voltage.
As a device which suppresses the above variations in threshold, a nonvolatile semiconductor memory disclosed in Japanese Patent Application (Heisei) No. 6-222734 filed by the same applicant as that of the present application on Aug. 25, 1994 is available. This Japanese patent application corresponds to U.S. patent application Ser. No. 08/516,830 filed on Aug. 18, 1995. According to the invention of this preceding application, variations in threshold of many memory cell transistors can be greatly suppressed.
According to the invention of this preceding application, after electrons are extracted from the floating gates of a memory cell transistor, the bit line potential varies. This variation in potential may influence the subsequent circuit operation somehow (decreasing the set potential precision in a sub bit line precharge operation).